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EM250
Table 24. SC2 SPI Master Mode Formats
SC2_SPICFG
Frame Format
2
1
0
0
0
SC2-3M
mode
MSCLK out
MOSI out
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
MISO in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
2
1
0
0
1
SC2-3M
mode
MSCLK out
MOSI out
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
MISO in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
2
1
0
1
0
SC2-3M
mode
MSCLK out
MOSI out
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
MISO in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
2
1
0
1
1
SC2-3M
mode
MSCLK out
MOSI out
TX[7]
TX[6]
TX[5]
TX[4]
TX[3]
TX[2]
TX[1]
TX[0]
MISO in
RX[7]
RX[6]
RX[5]
RX[4]
RX[3]
RX[2]
RX[1]
RX[0]
2
1
1
-
-
SC2-3M
Same as above except LSB first instead of MSB first
mode
2
1
-
-
-
SC2-4S
Illegal
mode
2
1
-
-
-
SC2-2 mode
Illegal
Serialized SC2 SPI transmit data is driven to the output pin MOSI. SC2 SPI master data is received from the
input pin MISO. To generate slave select signals to SPI slave devices, other GPIO pins have to be used and their
assertion must be controlled by software.
Characters transmitted and received are passed through transmit and receive FIFOs. The transmit and receive
FIFOs are 4 bytes deep. These FIFOs are accessed under software control by accessing the SC2_DATA data
register or under hardware control using a DMA controller.
When a transmit character is written to the (empty) transmit FIFO, the register bit SC_SPITXIDLE in the
SC2_SPISTAT register clears and indicates that not all characters are transmitted yet. Further transmit
characters can be written to the transmit FIFO until it is full, which causes the register bit SC_SPITXFREE in
the SC2_SPISTAT register to clear. After shifting out one transmit character to the MOSI pin, space for one
transmit character becomes available in the transmit FIFO. This causes the register bit SC_SPITXFREE in the
SC2_SPISTAT register to get set. After all characters are shifted out, the transmit FIFO empties, which causes
the register bit SC_SPITXIDLE in the SC2_SPISTAT register to get set also.
Any character received is stored in the (empty) receive FIFO. The register bit SC_SPIRXVAL in the
SC2_SPISTAT register is set to indicate that not all received characters are read out from receive FIFO. If
software or DMA is not reading from the receive FIFO, the receive FIFO will store up to 4 characters. Any
further reception is dropped and the register bit SC_SPIRXOVF in the SC2_SPISTAT register is set. The RX
FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the error
condition until the RX FIFO is drained. Once the DMA marks a RX error, there are two conditions that will clear
120-0082-000V Rev 1.1
Page 62
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